Method for fabrication of semiconductor device

ABSTRACT

A novel method is presented to provide ASICs with drastically reduced NRE and with volume flexibility. The invention includes a method of fabricating an integrated circuit, including the steps of: providing a semiconductor substrate, forming a borderless logic array including a plurality of Area I/Os and also including the step of forming redistribution layer for redistribution at least some of the Area I/Os for the purpose of the device packaging. The fabrication may utilize Direct Write e-Beam for customization. The customization step may include fabricating various types of devices at different volume from the same wafer.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application No.10/321,669, filed on Dec. 18, 2002 (to issue as U.S. Pat. No.6,953,956), commonly assigned, and incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to logic arrays and fabrication method forcustom integrated circuit

2. Discussion of Background Art

Semiconductor manufacturing is known to improve device density inexponential manner over time, but such improvements do come with aprice. The cost of mask set required for each new process technology hasbeen increasing exponentially. In addition, the minimum fabricationquantity due to the increases of wafer size has also increasedexponentially at the same time.

These changes represent an increasing challenge primarily to customproducts, which tend to target smaller volume and less diverse market,therefore making the increased cost of product development and reductionof manufacturing flexibility very hard to accommodate.

Custom Integrated Circuits can be segmented into two groups. The firstare devices that have all their layers custom made. The second group aredevices that have at least some generic layers used across differentcustom products. Well known examples of the second kind are Gate Arrays,which use generic layers for all layers up to contact layer, and FPGAswhich utilize generic layers for all their layers. This second group ofcustom integrated circuits is also sometimes called semi-custom devicesdue to their broader applicability. The generic layers in such devicesare mostly a repeating pattern structure in array form.

The use of generic layers across multiple application provides savingfor the individual custom product with respect to the cost of masks andeconomies of scale. In 1996 Chip Express of Santa Clara, Calif.,introduced a logic array called CX2000 that utilized a base logic cellequivalent to about 4 logic gates. At a later time LightspeedSemiconductor of Sunnyvale, Calif., introduced their 3G Modular Arrayproduct family. These more advanced logic arrays use generic layers,comprising mostly repeating pattern, also for some of the metal layerssuch as contact, Metal-1, Via-1 and Metal-2. These types of logic arraysare sometime called Module Arrays and require less custom layers. A veryadvanced Module Array technology was introduced by eASIC of San Jose,Calif., in September 2000.

That Module Arrays uses generic layers such as Metal-1 and Metal-2 todefine the logic array, in conjunction with generic layers such asMetal-3 and Metal-4 to provide a generic connectivity fabric. Thegeneric connectivity fabric comprises of repeating patterns and are alsostructured in array form. Such arrangement allows to further reduce thenumber of custom layers required for design customization. eASICtechnology, as described in U.S. Pat. No. 6,331,790 is going furthertoward the goal minimizing the number of custom masks and requires onlya single custom via mask.

The logic array technology is based on a generic fabric that iscustomized for a specific design during the customization stage. Asdesigns tend to be highly variable in the amount of logic and memoryeach one needs, vendors of logic array create product families with anumber of Master Slices covering a range of logic and memory sizeoptions. Yet, it is always a challenge to come up with minimum set ofMaster Slices that will provide a good fit for maximal number ofdesigns.

U.S. Pat. No. 4,733,288 issued to Sato Shinji Sato in March 1988,discloses a method “to provide a gate-array LSI chip which can be cutinto a plurality of chips, each of the chips having a desired size and adesired number of gates in accordance with a circuit design.” The priorart in the references cited presents few alternative methods to utilizegeneric structure for a different size of custom devices.

The array structure fits the objective of variable sizing. Thedifficulty to provide variable-sized devices is due to the need ofproviding I/O cells and associated pads to connect the device to thepackage.

U.S. Pat. No. 5,217,916 issued to Anderson et al. on Jun. 8, 1993,discloses a configurable gate array free of predefinedboundaries—borderless—using transistor gate cells, of the same type ofcells used for logic, to serve the input and output function.Accordingly, the input and output functions may be placed to surroundthe logic array sized for the specific application. This method presentsa severe limitation on the I/O cell to use the same transistors as usedfor the logic and would not allow the use of higher operating voltagefor the I/O.

It is also known in the art that I/O and pads do not need to be at theedge of the semiconductor device. Semiconductor devices could be usingthe flip chip or C-4 (controlled collapse chip connection) technologydescribed in U.S. Pat. Nos. 3,401,126 and 3,429,040 by Miller that hadbeen used for over 30 years in IBM's mainframe computer modules. Inthese approaches the bonding pads are deployed in an area array over thesurface of the chip known as area bonding and may use I/O cells known asarea I/O placed near the area pads. Flip Chip packaging is known in theart to use an additional final metal layer known as the redistributionlayer, to allow proper distribution of the device I/O to the area pads.

SUMMARY OF THE INVENTION

The present invention seeks to provide a new method for semiconductordevice fabrication that is highly desirable for custom products. Thecurrent invention suggests the use of direct-write e-Beam in conjunctionwith a continuous logic array. The continuous array utilizes area I/Owith area pads to allow variable sizing of designs and placing them on awafer with various numbers of repetitions. The current inventionprovides solution to the challenge of high cost of mask-set and lowflexibility that exist in the currently-common method of semiconductorfabrication. An additional advantage of the invention that it reducesthe high cost of manufacturing the many different mask sets required inorder to provide acceptable range of master slices. The currentinvention improves upon the prior art in many respects, including theway the semiconductor device is structured and those related to methodsof fabrication of semiconductor devices.

The prior art reflected the motivation to better fit the device size tothe custom application and therefore saving on wasted silicon. Thecurrent invention reflects the motivation to save the cost of mask withrespect to the investment that would have been otherwise required to putin place proper set of master slices. The current invention also seeksto provide the ability to incorporate memory block in the custom device.The current invention provides a method to customize the device withrespect the amount of logic and memory required.

The main point of the current invention is the use of area I/O toprovide a continuous fabric that provides a continuous terrain of logicand I/O and also provides the ability to mix in continuous terrain ofmemory with islands of special functions like PLL and SERDES. Thecurrent invention shows that with area I/O and redistribution layer toconnect the area I/O to area pads, many of the limitation of the priorart are overcome. A greater level of flexibility is therefore provided.The current invention also suggests to utilize Module Array, wherebyadditional layers such as Metal-1 and Metal-2 are generic and would bepart of such borderless continuous terrain. Furthermore, the currentinvention also suggests the use of segmented routing whereby some of theconnectivity layers are also generic and would be a part of thecontinuous terrain. In such fabric only few layers need to be customizedwhile most of the layers are generic and consist primarily of arepeating pattern. A favorable embodiment of the current invention is acontinuous terrain customizable by single custom via layer. Furthermore,the current invention suggests the use of direct-write e-Beam for thosefew custom layers. An added advantage of the current invention is theuse of direct-write e-Beam on the continuous terrain to provide on thesame wafer different product types, with different amount of productunits of the various product types. The very large size of current waferallows hundreds of device units, each of different type, built on asingle wafer. Therefore the current invention allows to provide“on-demand” semiconductor device manufacturing, where one customerscould get few units of one type of device for prototype work, whileanother may get few hundreds of devices for low volume production, allfrom a single wafer fabrication process.

To allow such level of flexibility with borderless terrain, the currentinvention suggests wafer level customization using equipment likedirect-write e-Beam and dicing the wafer using highly flexible dicingusing equipment like laser-based dicing. Such equipment allows mix andmatch of various die sizes on the wafer, as opposed to the saw dicingcommonly used in the industry, which requires dicing along completestraight lines from one wafer edge to the other. An added advantage ofthe current invention's is the use of area pads and homogenous padterrain so single probe card could be use for various devices.

The present invention also seeks to provide an improved semiconductordevice including borderless logic array; area I/Os; and a redistributionlayer for redistributing at least some of the area I/Os.

Preferably some of the pads are used to connect the semiconductor deviceto other devices and overlays at least a portion of the logic array or aportion of the area I/Os.

Preferably the semiconductor device also includes a borderless memoryarray. Preferably the logic array includes a module array. Preferablythe logic array includes interconnections within the logic array,wherein the logic array interconnections include metal layers and vialayers, and wherein at least one of the metal layers includes at leastone substantially repeating pattern for a portion used for theinterconnections. And according to one embodiment of the invention, thelogic array interconnection includes at least two of metal layers withsubstantially repeating patterns for portions used for interconnections.And according to another embodiment of the invention, the logic arrayinterconnection includes at least three metal layers with substantiallyrepeating patterns for portions used for the interconnections.Preferably the area I/Os are positioned in a non-surrounding fashionwith respect to the logic array. Preferably, the logic array includes arepeating module, and wherein the area I/Os are positioned in anon-surrounding fashion with respect to at least one of the repeatingmodule. Preferably at least one of the area I/Os is a configurable I/O.

There is thus provided in accordance with a preferred embodiment of theinvention, a method of fabricating a semiconductor device, comprisingthe steps of: providing a semiconductor substrate; forming a borderlesslogic array, including a plurality of area I/Os, on the semiconductorsubstrate; and forming a redistribution layer for redistributing atleast some of the area I/Os.

Preferably also including the step of: forming pads to connect thesemiconductor device to other devices, and wherein at least one of thepads overlays at least a portion of the logic array or a portion of thearea I/Os.

Preferably also including the steps of: placing and routing a specificdesign on the logic array; and marking marks for an edge of a usedportion of the logic array according to the step of placing and routing.

Preferably the step of marking comprises photolithography, and alsoincluding a step of dicing the semiconductor substrate according to themarks.

Preferably the step of dicing includes laser dicing.

There is thus provided in accordance with another preferred embodimentof the invention, a method of fabricating an integrated circuit,comprising the step of: Providing a semiconductor substrate, forming aborderless logic array including a memory array, a plurality of areaI/Os and also including the step of forming redistribution layer forredistribution at least some of the area I/Os for the purpose of thedevice packaging.

Preferably also including the steps of: placing and routing a specificdesign on the logic array and the memory array; and marking marks for anedge of a used portion of the logic array and the memory array accordingto the step of placing and routing.

Preferably the step of marking, includes photolithography, and alsoincluding a step of dicing the semiconductor substrate according to themarks.

Preferably the step of dicing includes laser dicing.

There is thus provided in accordance with another preferred embodimentof the invention, a method of fabricating an integrated circuit,comprising the step of: providing a semiconductor substrate, forming aborderless logic array including, a plurality of area I/Os and alsoincluding the step of forming redistribution layer for redistribution atleast some of the area I/Os for the purpose of the device packaging andwherein the logic array includes a module array.

There is thus provided in accordance with another preferred embodimentof the invention, a method of fabricating an integrated circuit,comprising the step of: Providing a semiconductor substrate, forming aborderless logic array including a plurality of area I/Os and alsoincluding the step of forming redistribution layer for redistribution atleast some of the area I/Os for the purpose of the device packaging, andwherein the logic array is interconnected by metal layers and vialayers, and wherein at least one of the metal layers comprises at leastone substantially repeating pattern for a portion used forinterconnecting.

And according to one embodiment of the invention, at least two of themetal layers include substantially repeating patterns for portions usedfor interconnecting.

And according to another embodiment of the invention, at least three ofthe metal layers comprise substantially repeating patterns for portionsused for the interconnecting.

There is thus provided in accordance with a preferred embodiment of theinvention, a method of fabricating a semiconductor device, comprisingthe steps of: providing a semiconductor substrate; forming a borderlesslogic array, including a plurality of area I/Os, on the semiconductorsubstrate; and forming a redistribution layer for redistributing atleast some of the area I/Os. And also includes the step of utilizing adirect write technique to customize the logic array.

Preferably the step of marking utilizes a direct write technique.

There is thus provided in accordance with a preferred embodiment of theinvention, a method of fabricating a semiconductor device, comprisingthe steps of: providing a semiconductor substrate; forming a borderlesslogic array, including a plurality of area I/Os, on the semiconductorsubstrate; and forming a redistribution layer for redistributing atleast some of the area I/Os, and wherein the step of forming aborderless logic array comprises the step of positioning the area I/Osin a non-surrounding fashion with respect to the logic array.

There is thus provided in accordance with another preferred embodimentof the invention, a method of fabricating a semiconductor device,comprising the steps of: providing a semiconductor substrate; forming aborderless logic array, including a plurality of area I/Os, on thesemiconductor substrate; and forming a redistribution layer forredistributing at least some of the area I/Os, and wherein the logicarray includes a repeating core, and wherein the step of forming aborderless logic array includes the step of positioning the area I/Os ina non-surrounding fashion with respect to at least one of the repeatingcore.

Preferably at least one of the area I/O is configurable I/O.

Preferably also including the step of: performing photolithography,wherein a reticle is projected over the semiconductor substrate, andwherein the used portion comprises elements from two projections.

There is thus provided in accordance with a preferred embodiment of theinvention, a method of fabricating an integrated circuit wafer,comprising the steps of: providing a semiconductor substrate; forming aborderless logic array, including a plurality of area I/Os, on thesemiconductor substrate; and forming a redistribution layer forredistributing at least some of the area I/Os.

Preferably also comprising the step of: forming pads to connect thesemiconductor device to other devices, wherein at least one of the padsoverlays at least a portion of the logic array or a portion of the areaI/Os.

Preferably also including the steps of: placing and routing a specificdesign on the logic array; and marking marks for an edge of a usedportion of the logic array according to the step of placing and routing.

Preferably the step of marking comprises photolithography, and alsoincludes a step of dicing the semiconductor substrate according to themarks.

Preferably the step of dicing includes a step of laser dicing.

There is thus provided in accordance with a preferred embodiment of theinvention, a method of fabricating an integrated circuit wafer,comprising the steps of: providing a semiconductor substrate; forming aborderless logic array, including a memory array, a plurality of areaI/Os, on the semiconductor substrate; and forming a redistribution layerfor redistributing at least some of the area I/Os.

Preferably also comprising the steps of: placing and routing a specificdesign on the logic array and the memory array; and marking marks for anedge of a used portion of the logic array and the memory array accordingto the step of placing and routing.

Preferably the step of marking comprises photolithography, and alsocomprising a step of dicing the semiconductor substrate according to themarks.

Preferably the step of dicing includes laser dicing.

Preferably the logic array includes a module array.

Preferably the logic array is interconnected by metal layers and vialayers, and wherein at least one of the metal layers includes at leastone substantially repeating pattern for a portion used forinterconnecting.

Alternatively at least two of the metal layers include substantiallyrepeating patterns for portions used for the interconnecting.

Preferably the step of placing and routing is done for a specific designcalled A′ and also for another specific design called B′, and whereinthe location on the wafer in which design A′ is placed is independent ofthe location on the wafer in which design B′ is placed.

Alternatively the step of placing and routing is done for a specificdesign called A′ and also for another specific design called B′, andwherein a number of times that design A′ is placed on the wafer isindependent of a number of times that design B′ is placed on the wafer.

Preferably the step of marking includes the step of utilizing a directwrite technique.

Preferably the step of placing and routing is done for a specific designcalled A′ and also for another specific design called B′, and wherein asilicon area ratio of logic array to memory array in design A′ issubstantially larger than a silicon area ratio of logic array to memoryarray in design B′.

Preferably the step of marking includes the step of utilizing a directwrite technique.

Preferably also including the step of probing the wafer, wherein thestep of probing utilizes the same wafer probe to test design A′ anddesign B′.

Preferably also comprising the step of probing the wafer, wherein thestep of probing utilizes the same wafer probe to test design A′ anddesign B′.

Preferably also comprising the step of probing the wafer, wherein thestep of probing utilizes the same wafer probe to test design A′ anddesign B′.

Preferably also comprises the step of utilizing a direct write techniqueto customize the logic array.

Preferably the design A′ and design B′ are probed simultaneously.

Preferably design A′ and design B′ are probed simultaneously.

There is thus provided in accordance with additional preferredembodiment of the invention, a method of fabricating an integratedcircuit wafer with improved yield, comprising the steps of: providing asemiconductor substrate; forming a borderless logic array, including aplurality of area I/Os, on the semiconductor substrate; and forming aredistribution layer for redistributing at least some of the area I/Os,and further comprising the steps of: testing and marking modules on thelogic array; placing specific designs on the logic array so as to avoidfaulty modules; and customize the logic array according to placement ofspecific designs; testing and marking the specific designs; and dicingthe logic array according to placement and marking of specific designs.

Preferably utilizing a direct write technique to customize the logicarray.

Preferably having one or more pads dedicated to testing.

Preferably also including the step of using a probe card toindependently test one or more modules simultaneously.

Preferably one or more of the pads dedicated to testing are not the areaI/Os for the specific designs.

Preferably at least one of the area I/Os comprises a configurable I/O.

Preferably the configurable I/O comprises multiple copies of input,output, and pre-output cells, and wherein the semiconductor devicefurther comprises connections between at least one of the input, output,and pre-output cells and area I/O pads to construct an area I/O.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be understood and appreciated more fully fromthe following detailed description, taken in conjunction with thedrawings in which:

FIG. 1 is a drawing illustration of a wafer marked with reticleprojections;

FIG. 2, consisting of FIGS. 2-1, 2-2, and 2-3, is a drawing illustrationof a repeating core;

FIG. 3A is a drawing illustration of a area pads;

FIG. 3B is a pictorial illustration of a area pads—soldering balls;

FIG. 3C is a pictorial illustration showing the use of a redistributionlayer to connect area I/O to edge pads;

FIG. 4 is a detail drawing illustration of the area pads;

FIG. 5 is a drawing illustration of a wafer level borderless logicarray;

FIG. 6 is a drawing illustration of a wafer shared between twoapplications utilizing reticle sharing;

FIG. 7 is a drawing illustration of a wafer shared between twoapplications;

FIG. 8 is a drawing illustration of a wafer shared between threeapplications;

FIG. 9A is a drawing illustration of a reticle fabric;

FIG. 9B is a drawing illustration of a reticle fabric;

FIG. 9C is a drawing illustration of a reticle fabric;

FIG. 10A is a drawing illustration of a reticle fabric;

FIG. 10B is a drawing illustration of a reticle fabric;

FIG. 11 is a drawing illustration of a reticle fabric;

FIG. 12 is a drawing illustration of a wafer marked with reticleprojections;

FIG. 13 is a drawing illustration of a module;

FIG. 14 is a drawing illustration of a wafer comprise wafer levelborderless logic array covered with Area Pads;

FIG. 15 is a drawing illustration of via customizable routing structure;

FIG. 16 is a drawing illustration of via customizable I/O;

FIG. 17 is a drawing illustration of via customizable I/O customized asinput;

FIG. 18 is a drawing illustration of via customizable I/O customized asoutput;

FIG. 19 is a layout drawing illustration of via customizable I/O;

FIG. 20 is a layout drawing illustration of a small section of viacustomizable I/O;

FIG. 21, consisting of FIGS. 21-1, 21-2, and 21-3, is a drawingillustration of very long tracks over a core;

FIG. 22 is a drawing illustration of a configurable buffer structure;

FIG. 23 is a drawing illustration of a simple “scramble box;”

FIG. 24 is a drawing illustration of “scramble box” layout; and

FIG. 25 is a drawing illustration of “scramble box: layout for 24 lines.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention is now described with reference to FIGS. 1-25, itbeing appreciated that the figures illustrate the subjects matter not toscale or to measure.

The current method of semiconductor fabrication is on lithography stepfor each layer. The dominating lithography technique of submicronprocess is called step and repeat. The layer pattern will be drawn intomask also called reticle. Such reticle may be projected over an area ofabout 20 mm×20 mm by the lithography tool called Stepper. Then theStepper steps the wafer so the reticle would be projecting the samepattern on area next to it and so for. FIG. 1 illustrates a wafer 8 withmarks 12 of reticle projections 10. With an 8-inch wafer, over 50 copiesof the reticle will be typically stepped on one such wafer.

The current invention suggests the use of a much less common lithographytechnique called direct-write using e-Beam. Such could be done, forexample, with direct-write e-Beam—Leica ZBA32 offered by LeicaMicrosystems Lithography GmbH Jena, Germany or F5112 offered byAdvantest, Japan. Direct-write e-beam allows direct writing any patternat any location over the wafer, without the use of a physical mask.Direct-write e-beam is not used in commercial fabrication ofsemiconductor devices due the low throughput and the implication of suchon a single wafer cost. The current invention suggests the combinationof reticle technique for the generic portion of logic array and the useof direct-write e-beam for the custom layers. A very good fit with thismethod is the logic array invented by eASIC, as only it provides a logicarray that could be customized with single via layer. Via layer can bewritten much faster than metal layer with direct-write e-beam and wouldmake such combination method commercially viable.

Such direct-write e-beam fabrication method are highly attractive forcustom designs as previously described. Since single wafer may have roomfor hundreds of devices, the current invention seeks to allow multipledesigns to be placed on one wafer and further, to allow each of thesedesigns to be of different size and, even further, to allow placingdifferent quantities of such designs on a single wafer, to support onone wafer the fabrication needs of both prototype volumes for somedesign and pre-production volumes for other designs.

While direct-write e-Beam is the most common technique, otherdirect-write lithography could be used. A laser mask write systems likeSigma 7000 from Micronic could be modified for such usage.

The current invention suggests a new architecture of logic array. Thisnew architecture blends logic array with array of area I/O and array ofarea pads. Therefore it provides a continuous fabric instead of themaster slice approach. Such fabric could comprise of a repeatingstructure—repeating core—as is illustrated in FIG. 2. The repeating core28 comprises a set of area I/O 26 and then logic array 24 which isconstructed from array of eCells 22. The area I/O may be constructedwith thick oxide to allow them to operate at higher voltage appropriateto interface with the element outside the device, while the logic arraymight be using thin oxide to operate at low voltage to reduce powerconsumption and allow higher performance and packing density. The areaI/O might comprise elements that are common at boundary I/O such as ESDprotection and latch-up protection. The area I/O could be configurableI/O that could be customized to the specific function by the customlayers used to customize the logic. The area I/O could include fixedfunction like input and output functions. The power supply to the core28 and to the area I/O 26 could be supplied from the same group of areapads.

FIG. 3 is a drawing and pictorial illustration of the area pads. FIG. 3Ais a vertical cut drawing showing one area pad and the associated bump30, and the layers underneath it including a thick layer 32 sometimescalled redistribution layers and the underlying layers such as Metal-134, Metal-2 36 and Metal-4 38. FIG. 3B is a pictorial of section of thetop surface of a device according to the current invention, with aregular array of area pads in the forms of bumps 39. FIG. 4 is adetailed drawing illustration of an area pads and sample sizes for suchbumps. To maximize the number of pads per area, it is common to placethe area pads in a regular array as can be seen in FIG. 3B. Consequentlyit is useful to have a top metal layer for pads redistribution, to allowarea pads placement to be independent from area I/O placement.

This invention suggests a fabric of a repeating core which includelogic, area I/O, and area pads. The minimum size of such core would beto fit single area pads like 3A. In most cases a larger size core wouldbe more practical. The core 28 of FIG. 2 is about 1 mm×0.5 mm in 0.13micron process. It would be quite possible to provide 4×2 area pads andthe appropriate number of area I/O with it. Tilling such core to span afull wafer will allow a fabric of borderless logic array of about 20×40cores 28 in one reticle. If the accuracy of the stepper is high enough,it would be conceivable that the borderless fabric could be extended upto wafer level. In such case it may require somewhat less denselithography pitch for the routing structures, to allow spanning acrossreticle boundaries. The wafer level borderless fabric provides hehighest level of flexibility and wafer utilization effectiveness. Forthe ease of description, the following detailed description of theadditional preferred embodiments of this invention assumes wafer levelborderless logic array. FIG. 5 is a drawing illustration of a wafer 50comprising of wafer level borderless logic array of continuous tillingof cores 52.

The redistribution layer may also be a custom layer. It could thereforebe custom designed to redistribute the area I/O to the edge pads in aspecific design and therefore allow such custom design to be packagedusing conventional bonding rather than Flip-chip. FIG. 3C illustratesthe use of redistribution layer 32 to connect area I/O 36 to edge pads34 so wire bonding could be used.

FIG. 6 is a drawing illustration of a wafer shared between two designsutilizating reticle sharing. FIG. 6 illustrates the existing art ofreticle sharing wherein one reticle may include design A′ 62 which isplaced and routed on the logic array and occupies a large portion of thereticle, and design B′ 64 that is smaller and could be placed two timeswithin the reticle, so together with design A′ the reticle is fullyutilized. Design A′ edges are marked by marks 63 and 66 and design B′edges are marked by marks 65, 66 and 67.

It might be highly desirable to have these edges 63, 65 marked bylithography and following process to allow proper dicing of the wafer.Such marking would be best done at the top or very close to the toplayer and prior to the bump processing step. Such marking step is notusually required for logic array where the master slice are arranged forspecific array size and the boundary pads, together with the spacebetween devices, make it very visible where dicing should take place.

It is clear that conventional saw dicing would be proper for dicing thewafer 60 from design A′ point of view. Yet the edge 67 would be left tobe diced at a later stage to separate the two dies of design B′.

The current invention provides the ability to size each designindependently and to mix different designs on single wafer. Constrainingdicing along straight continuous lines places a strong limitation on theability to share one wafer with multiple-sized designs. It is thereforesuggested to use laser dicing for wafers fabricated according to thecurrent invention. Laser dicing is being developed and offered by fewcompanies such as DFL7160 made by Disco Corporation Tokyo, Japan, andMultidice made by NanoVia, LP of Londonderry, N.H. Thinning the back ofthe wafer may be required so laser dicing would allow for a full cutrather than just scribing.

In another embodiment of the current invention, a very flexible wafersharing is suggested. Such wafer sharing provides much higherflexibility than reticle sharing. FIG. 7 is a drawing illustration of awafer shared between two applications taking advantage of the borderlessarray, together with the use of direct-write for wafer levellithography. It is therefore possible to mix different designs atvarious quantities on such wafer. FIG. 7 illustrates design 72 placedfor prototype stage, while another design 74 is placed many more times.Unlike the case with reticle sharing, the locations and the number oftimes one design is placed on a wafer has little bearing on the otherdesign. An important advantage of this invention is that the location onthe wafer in which one design is placed, is independent to the locationon the wafer in which a second design is placed, other than the obviouslimitation that it can not be placed in location already taken by thefirst design. More importantly, the number of times one design is placedis independent to the number of times the other design is placed.

FIG. 8 is a drawing illustration of a wafer 80 shared between threeapplications. Design 82 has three sites on the wafer, which representprototype level. Designs 84 and 86 have tens of locations assigned tothem. It is clear that the location and the number of sites for design86 are independent on those of design 82. In addition it should be notedthat many of the dicing lines 88 do not extend from one edge of thewafer 80 to the other edge. Dice lines 88 do not fit saw dicing, butrather require the use of a flexible dicing approach such as laserdicing.

Many logic arrays are now offering logic fabric with additionalfunctional blocks such as memory blocks, processors or special elementslike PLL. Typically the embedded memory takes the second largest portionof the master slice area after the logic array. In general embeddedmemories are constructed as a small array of configurable memory blocks.The custom design may need certain amount of memory or some number ofPLL and so forth. It is an increasing challenge to select the rightmaster-slice combination, since designs with similar amounts of logicmay require very different amounts of memory.

In yet another embodiment of the current invention, the continuous logicarray fabric is comprised of a continuous logic array and continuousmemory array of small memory blocks. It therefore now possible that aspecific design will be placed on a section of such continuous fabric,sized to have exactly the desired amount of logic and the desired amountof memory.

FIG. 9 is a drawing illustration of a reticle 90 fabric comprising ofcontinuous logic array 92 and memory array 94. FIG. 9A illustrates acustom design placed on such terrain as marked by the rectangle 96 tohave no memory. FIG. 9B illustrates a custom design placed on suchterrain as marked by the rectangle 97 to have some memory. FIG. 9Cillustrates a custom design placed on such terrain as marked by therectangle 98 to have a small amount of logic and all the rest memory.FIG. 10A is a drawing illustration of a reticle fabric 100 wherein thememory terrain 104 is shaped in a staircase manner. FIG. 10B illustratesthat such staircase arrangement provides a higher level of flexibilitywith regards to the amount of memory blended into the rectangularmarkings of the custom design.

The advantage of continuous terrain is the ability to use one set ofgeneric masks to cover many variations of product fabrics, with theability to tailor the right amount of logic with the right amount ofmemory. The additional advantage is the ability to use one wafer run tomake a flexible mix of custom products. It is usually highly desirableto utilize the silicon area as effectively as possible. Yet it may oftenhappen that by tailoring the amount of logic and memory to the need of aspecific design, the tiling efficiency is compromised. The number ofdevices on one wafer would be at least the number of times the reticleis stepped over the wafer. If high volume production is required thencustom masks could be fabricated so volume production would be done atmaximum silicon utilization.

FIG. 11 is a drawing illustration of a reticle 110 of a logic array thatin addition to array of logic fabric comprises additional functionallogic elements like processor blocks 112, 113, 114, 115 and memory array118. FIG. 12 is a drawing illustration of a wafer 120 marked withreticle 110 projections. FIG. 12 illustrates the use of the waferterrain to carve out specific design 129 to include elements from fourdifferent reticle projections 124—four processors—with a portion of thememory array 128. By proper placing a specific design 129 on the waferterrain, it is possible to optimize the silicon area and yet provide adifferent mix of elements from one generic fabric.

The construction of borderless logic array according to the currentinvention should include consideration for wafer dicing. The common wayis to draw a scribe line indicating were the wafer will be scribed, toallow the dicing of the wafer into many individual dies. Typically alaser scribe can cut a 50 microns wide width, but it may be preferred toplan for scribing width between 75 to 100 microns wide. Preferably thecontinuous array is constructed as array of modules. A preferred moduleis rectangular with each side sized between 0.5 to 2 mm. A module couldbe array of logic or array of memory or combination thereof, which mayinclude other special function like PLL. A preferable location forscribe lines is the edge of such module. The location for potentialscribe line may include transistors, which would not be powered if thatscribe line is used for dicing. Alternatively it could be designed soonly connectivity structures are placed in the scribe lines designatedareas. FIG. 13 is a drawing illustration of a module 130 with designatedarea for scribe line 136 and customizable connection 134 to the scribeline routing fabric (not shown). The customizable connection 134 allowsdisconnection from the routing fabric at the scribe lines area, if thatpotential scribe line is designated for dicing. The repeating module 130comprises of pads 132 for the I/Os that are included in the module 130and pads 138 for the supply powering the circuits within the module.

Yet another advantage of the current invention is the possible use ofsingle Probe Card for multiple designs. FIG. 14 is a drawingillustration of a wafer comprised of wafer level borderless logic arraycovered with Area Pads. The pads area of the wafer is uniform and isindependent of the specific design size and placement. With suchregularity, it is possible to construct single probe card to allowtesting of the wafer by stepping over it. Under proper software controla single Probe Card could be used to test any device on the wafer 140.Similarly, it is also contemplated that a single Probe Card may be usedto simultaneously test multiple dies on the wafer, or with the propertest logic, test a die with more area pads than probes on the ProbeCard.

The current invention is not limited to products that combine genericlayers with custom layers. Rather it could be use to build a borderlessFPGA product. A borderless FPGA wafer could than be diced to providemany options of gate count and block memory size from one base mask-set.

Another use of the current invention is to yield a very large device.Very large devices are subject to very low yield, which make themeconomically unviable. Under the current invention yield can be improvedif the following procedure is applied:

-   -   (1) Test the substrate layers prior to the custom masks. This        implies that each module is independently tested. To do this        there need to be pads dedicated to some functions like clock,        scan-in, scan-out, and test control. Probe technology exists to        probe pads as small as 20×20 microns with minimal damage, though        special alignment equipment will probably need to be integrated        into existing standard Probers.    -   (2) Place the specific design so as to avoid faulty substrate        cells. This requires a special placement program, to make the        best use of the available wafer area given the outstanding        orders of dies to manufacture. Presumably this also controls the        designation of the direct write of the adapted for yield custom        via patterns.    -   (3) Dice the wafer accordingly.

The resulting system should provide significant yield improvement overexisting techniques. Rough analysis suggests that pre-testing anddynamic placement of die can double the revenue per wafer overconventional techniques, if a sufficiently wide range of die sizes arerequired for production. It should also be noted that, as with the othertechniques above, larger dies than are currently possible with existingstepper technology could be produced. In that case the described yieldenhancement is crucial.

It is further contemplated that the dedicated pads needed for testingmay or may not coincide with the area pads as shown in FIG. 3 c. It isalso contemplated that the pads necessary for testing may have the sameconfiguration regardless of the type of module, such that the probe cardmay be configured to simultaneously probe any combinations of modules ata time.

In another embodiment, test, power, ground and clock logic may be tiedtogether at the wafer level, such that a single probe of the wafer issufficient to test all of the modules within the wafer. Subsequentcustomization and scribing then isolates the power, ground, test andclock logic to specific modules and dies, to reduce the need for specialpads, and pre-customization test time.

FIG. 15 is a drawing illustration of via layer customizable routingstructure 150. In some fabrication processes a via layer might havereduce yield. A variation of the structure 150, that uses double via forthe continuation bridges 154 instead of single via 152, could be aneffective solution. Via customizable routing fabric increases the use ofvias primarily in the form of same direction connection utilizing smallbridges. Therefore bridges employing double vias are an effectivesolution. It should be pointed out that double via bridges imply cost,by reducing the number tracks available for routing.

An alternative solution could be employed for volume production. Itsuggests that in addition to the custom via layer, the two metal layerscould use custom mask that connect the segments 153, 155 with the samemetal layer 156.

For volume production additional yield enhancement technique could beemployed. For example, a software routine can inspect the custom designand replace any single via with a double via where possible. Having mostof the patterns in an array form with a highly repetitive structure makeit very friendly to employment of yield enhancements. It is possible tokeep track of yield loss in production of specific designs that utilizethe same logic array fabric. Any failure mechanism could then bereviewed for yield enhancement. The yield enhancement may involvechanging the layout of the generic logic array and therefore replacingsome of the generic masks.

Reference is now made to FIGS. 16, 17, and 18 which illustrate anotherpreferred embodiment of the current invention. These figures illustratevia-configurable I/O. Preferably the area I/O of the borderless logicarray is configurable I/O. It is advantageous to many users to haveflexibility of the I/O configuration, in addition to having flexibilityof the logic. It is the purpose of this invention to utilize the samecustom mask to configure both the core logic and the I/O. FIG. 16illustrates a simple via-configurable I/O 160, where the potential viaare marked by a circle 162. Few vias are arranged to connect a line usedas a jumper, and mark such as J4 164 to the crossing line, preferablyunderneath 166 or 167 or 168. Different types of I/Os could beconstructed by selecting some of the potential vias. FIG. 17 presents aconfiguration of the configurable I/O of FIG. 16 as an input cell 170.The selected vias are marked by black filled circle 172. FIG. 18presents an alternative configuration as output cell 180.

FIG. 19 is a layout drawing illustration of via customizable I/O 190.The I/O comprises the main elements pads 192, high drive I/O section 194and the I/O logic section 196 comprising the pre-I/O circuits.

FIG. 20 is a layout drawing illustration of a small section of the viacustomizable I/O. Illustrating a jumper 202 with via activated 204 andvia not activated 206

In another embodiment I/O may be comprised of many input 163, output 165or pre-output 161 cells such that most I/O types could be constructed byinterconnecting to one or more of these cells by providing additionalsegments between cells for via programming. It is further contemplatedthat many more I/O cells 26 exist in each repeating core 28, FIG. 2,than area pads in each repeating core, to allow flexible programming ofeach repeating core's I/O pads.

In another embodiment of this current invention additional routingchannels, called very long tracks, are introduced. Reference is now madeto FIG. 21. FIG. 21 is a drawing illustration of very long tracks 212,214 across a module 210. The very long tracks could go under or over thelocal routing fabric 150 to allow segmented routing of more than 4 metallayers. When many modules are tiled together to construct array of logicwith over million gates, more than 4 layers of routing might berequired. The current invention suggests the use of very long tracks inaddition to the short tracks and long tracks described in U.S. Pat. No.6,331,733. The very long tracks would have very few, or even no, contactwithin the module. The router software could assign the very long tracksto route between logic cells that are very far apart. At every end pointor contact point of the very long track, short routing tracks would beused to connect it to the 4-metal routing fabric. This approach allowsextension of the segmented routing architecture to as many metal layersas the fabrication process supports. It is further contemplated thatvery long tracks will include jumpers 154, an example of which is shownin FIG. 15, between each repeating core, to allow for scribing betweenrepeating cores while maintaining reliable use of all segments. Inaddition, it is contemplated that some of these long lines may be usedfor power and ground distribution across modules within target dies.

In another embodiment of the current invention a “scramble box” isproposed for the routing connection between modules 190. The objectiveof such “scramble box” is to reduce cross talk between lines. By havingsuch “scramble box” be part of the generic fabric the solution isprovided in the fabric rather than by careful design of thecustomization layers. Preferably such a “scramble box” would includebuffers to further simplify the customization. Reference is now made toFIG. 22. FIG. 22 is a drawing illustration of a configurable bufferstructure. Numeral 220 illustrates a via configurable buffer structure.It includes a buffer 229 that has in the lower layers two Metal 7jumpers 225, 226 and four Metal 6 connection lines. By selecting two orfour vias the structure could be configured for:

-   -   (1) Buffer line 222 to line 224;    -   (2) Buffer line 224 to line 222;    -   (3) Connect line 222 with line 224 with no buffer and tie off        the buffer;    -   (4) Leave lines 222 and 224 unconnected and tie off the buffer.

FIG. 23 is a drawing illustration of a simple “scramble box” in whichfour lines are coming into the “scramble box” 230 to one side 232 andcoming out from the other side 234; each line is now next to a new line.

FIG. 24 is a drawing illustration of a “scramble box” layout. Thefour-lines “scramble box” 240 includes a configurable buffer structure242.

FIG. 25 is a drawing illustration of a “scramble box” layout for 24lines 250. It comprises six repetitions of the structure 240.

It will be appreciated by persons skilled in the art that the presentinvention is not limited by what has been particularly shown anddescribed hereinabove. Rather, the scope of the present inventionincludes both combinations and sub-combinations of various featuresdescribed hereinabove as well as modifications and variations whichwould occur to persons skilled in the art upon reading the foregoingdescription and which are not in the prior art.

1.-62. (canceled)
 63. A device comprising: a borderless logic array;area I/Os; a redistribution layer to redistribute one or more of saidarea I/Os; and at least one pad to connect said device to at least oneother device, wherein at least one said pad overlays at least a portionof the logic array or a portion of the area I/Os.
 64. The deviceaccording to claim 63, further comprising: a borderless memory array.65. The device according to claim 63, wherein said logic arraycomprises: a module array.
 66. A device comprising: a borderless logicarray, including one or more logic array interconnections, wherein saidone or more logic array interconnections comprise metal layers and vialayers, and wherein at least one of said metal layers comprises at leastone substantially repeating pattern for a portion used for said logicarray interconnections; area I/Os; and a redistribution layer.
 67. Thedevice according to claim 66, wherein at least two of said metal layerscomprise substantially repeating patterns for portions used for saidlogic array interconnections.
 68. A device according to claim 66,wherein at least three of said metal layers comprise substantiallyrepeating patterns for portions used for said logic arrayinterconnections.
 69. A device comprising: a borderless logic array;area I/Os positioned in a non-surrounding fashion with respect to saidborderless logic array; and a redistribution layer to redistribute atleast some of said area I/Os.
 70. A device comprising: a borderlesslogic array, the borderless logic array comprising a repeating module;area I/Os positioned in a non-surrounding fashion with respect to atleast one of said repeating modules; and a redistribution layer toredistribute at least some of said area I/Os.
 71. A device comprising: aborderless logic array, comprising a repeating core; area I/Os, at leastone of said area I/Os being a configurable I/O; and a redistributionlayer for redistributing at least some of said area I/Os.
 72. A devicecomprising: a borderless logic array; area I/Os, wherein at least one ofsaid area I/Os comprises a via-configurable I/O.
 73. The device as inclaim 72, further comprising: a redistribution layer for redistributingat least some of said area I/Os.
 74. A device comprising: a logic array;and via-configurable I/Os, wherein at least one of said via-configurableI/Os contains a structure to enable the via-configurable I/O to beconfigured in the following forms: as a single-ended input; as asingle-ended output; as a portion of a differential input pair; and as aportion of a differential output pair.